TRAINING

TRAINING

Surrogate gradients make backpropagation
work through discrete spike events.

The core obstacle in training spiking neural networks with gradient descent is the spiking non-linearity itself. The Heaviside step function H(x) — which converts membrane potential to a spike — has derivative zero almost everywhere and is undefined at x = 0. Backpropagation requires meaningful gradients at every layer; a binary-valued neuron kills them entirely.

Surrogate gradient methods resolve this by using a smooth approximation g′(x) in the backward pass only. The forward pass remains exact — neurons fire binary spikes according to H(mem − threshold) — but during backpropagation, the derivative of the spike function is replaced with a smooth proxy. This is not an approximation of the forward computation; it is an approximation of a learning signal.

THRINDEX uses the fast sigmoid surrogate:

The core obstacle in training spiking neural networks with gradient descent is the spiking non-linearity itself. The Heaviside step function H(x) — which converts membrane potential to a spike — has derivative zero almost everywhere and is undefined at x = 0. Backpropagation requires meaningful gradients at every layer; a binary-valued neuron kills them entirely.

Surrogate gradient methods resolve this by using a smooth approximation g′(x) in the backward pass only. The forward pass remains exact — neurons fire binary spikes according to H(mem − threshold) — but during backpropagation, the derivative of the spike function is replaced with a smooth proxy. This is not an approximation of the forward computation; it is an approximation of a learning signal.

THRINDEX uses the fast sigmoid surrogate:

g′(x) = β / (2 · (1 + β |x|) ² )

where β controls sharpness (THRINDEX default: β = 5.0). Higher β more closely approximates the true Heaviside but risks vanishing gradients far from threshold. Lower β gives smoother gradients at the cost of a weaker correspondence to the actual firing boundary. The deployed model uses the exact Heaviside — the surrogate never touches inference.

Practical implication: The surrogate gradient is a training artefact. It determines how well the model learns, not how it runs. Hyperparameter sensitivity is real: networks that train well under one surrogate may fail to converge under another, even with identical architecture and data.

where β controls sharpness (THRINDEX default: β = 5.0). Higher β more closely approximates the true Heaviside but risks vanishing gradients far from threshold. Lower β gives smoother gradients at the cost of a weaker correspondence to the actual firing boundary. The deployed model uses the exact Heaviside — the surrogate never touches inference.

Practical implication: The surrogate gradient is a training artefact. It determines how well the model learns, not how it runs. Hyperparameter sensitivity is real: networks that train well under one surrogate may fail to converge under another, even with identical architecture and data.

ENERGY

ENERGY

The energy advantage of spikes is quantitative and the arithmetic is straightforward.

Spiking networks are often described as "energy efficient" without the numbers being stated. The arithmetic is not complicated and should be in every neuromorphic engineer's head.

For a fully-connected layer with N_pre presynaptic neurons, N_post postsynaptic neurons, T timesteps, and mean spike rate r, the energy cost is:

Spiking networks are often described as "energy efficient" without the numbers being stated. The arithmetic is not complicated and should be in every neuromorphic engineer's head.

For a fully-connected layer with N_pre presynaptic neurons, N_post postsynaptic neurons, T timesteps, and mean spike rate r, the energy cost is:

E_snn = r × N_pre × N_post × T × ε_syn

E_ann = N_pre × N_post × T × ε_mac

where ε_syn ≈ 0.5 pJ/syn-op (Intel Loihi, published benchmark) and ε_mac ≈ 2.56 pJ/MAC (A100 GPU, MLPerf Power). The ratio at r = 0.10 is:

where ε_syn ≈ 0.5 pJ/syn-op (Intel Loihi, published benchmark) and ε_mac ≈ 2.56 pJ/MAC (A100 GPU, MLPerf Power). The ratio at r = 0.10 is:

η = (r × ε_syn) / ε_mac = (0.10 × 0.5) / 2.56 ≈ 0.020

A 51× energy advantage per synaptic operation. This does not account for the memory bandwidth savings from sparse event representation versus dense float activations, which can be the dominant cost at low spike rates.

The coefficient matters. ε_syn = 0.5 pJ/syn-op represents an achievable value on current silicon, not a theoretical minimum. Real devices vary: Intel Loihi 2 publishes ~5 pJ/syn-op under load; the 0.5 pJ figure comes from optimised inference measurements. THRINDEX's default coefficient is intentionally optimistic to represent the performance potential of the architecture, and should be calibrated per target with --energy-coeff.

A 51× energy advantage per synaptic operation. This does not account for the memory bandwidth savings from sparse event representation versus dense float activations, which can be the dominant cost at low spike rates.

The coefficient matters. ε_syn = 0.5 pJ/syn-op represents an achievable value on current silicon, not a theoretical minimum. Real devices vary: Intel Loihi 2 publishes ~5 pJ/syn-op under load; the 0.5 pJ figure comes from optimised inference measurements. THRINDEX's default coefficient is intentionally optimistic to represent the performance potential of the architecture, and should be calibrated per target with --energy-coeff.

QUANTIZATION

QUANTIZATION

Quantization gap: int8 is safe, int4 is not
and the boundary is measurable.

Deploying a trained SNN to neuromorphic silicon requires quantizing weights from float32 to a fixed-point integer format. The critical question — how much does this change the network's behavior? — has no universal answer. It depends on the model, the task, and the precision floor.

THRINDEX's conformance suite answers this empirically for a concrete model class. Running the reference simulator on 20 frozen fixtures (stratified across the SHD keyword-spotting task) at three precision levels:

Deploying a trained SNN to neuromorphic silicon requires quantizing weights from float32 to a fixed-point integer format. The critical question — how much does this change the network's behavior? — has no universal answer. It depends on the model, the task, and the precision floor.

THRINDEX's conformance suite answers this empirically for a concrete model class. Running the reference simulator on 20 frozen fixtures (stratified across the SHD keyword-spotting task) at three precision levels:

float32 → all 20 fixtures pass at reference tolerance

int8 → all 20 fixtures pass (per-channel symmetric)

int4 → 4/20 fixtures fail — a distinct, measurable quality gap

The conformance envelope thresholds (T_mean = 20 ms, T_max = 130 ms, P_min = 0.900) were placed 40% into the gap between int8 and int4 performance — conservative enough to certify current hardware, tight enough that int4-only backends cannot pass without an explicit exemption.

What this means in practice: A backend that passes CONFORMANCE_ENVELOPE_V0 has demonstrated int8-equivalent behavior on the reference task. It says nothing about int4 paths, novel neuron models, or tasks with different temporal statistics. The envelope is a floor, not a ceiling.

There is no published standard for neuromorphic conformance testing. The closest analogues — ONNX conformance, MLPerf inference — model neither temporal dynamics nor spike-rate-dependent energy. THRINDEX's conformance methodology is original work.

The conformance envelope thresholds (T_mean = 20 ms, T_max = 130 ms, P_min = 0.900) were placed 40% into the gap between int8 and int4 performance — conservative enough to certify current hardware, tight enough that int4-only backends cannot pass without an explicit exemption.

What this means in practice: A backend that passes CONFORMANCE_ENVELOPE_V0 has demonstrated int8-equivalent behavior on the reference task. It says nothing about int4 paths, novel neuron models, or tasks with different temporal statistics. The envelope is a floor, not a ceiling.

There is no published standard for neuromorphic conformance testing. The closest analogues — ONNX conformance, MLPerf inference — model neither temporal dynamics nor spike-rate-dependent energy. THRINDEX's conformance methodology is original work.

PORTABILITY

PORTABILITY

Every neuromorphic chip implements a slightly
different neuron. The differences are not cosmetic.

Cross-chip portability is the unsolved engineering problem in neuromorphic computing. A model trained and validated on one chip cannot be assumed to produce equivalent output on another — not because of software abstraction failures, but because the physical neuron dynamics differ at the specification level.

The differences that cause measurable behavioral divergence:

Reset semantics: subtract-from-threshold vs zero-reset
→ different membrane trajectories after every spike

Leak ordering: (leak → integrate → fire) vs (integrate → fire → leak)
→ numerical differences that compound across timesteps

Delay model: per-synapse vs per-layer vs none
→ different temporal structure in multi-layer networks

Weight precision: int8 vs int4 vs binary
→ different classification boundaries

Cross-chip portability is the unsolved engineering problem in neuromorphic computing. A model trained and validated on one chip cannot be assumed to produce equivalent output on another — not because of software abstraction failures, but because the physical neuron dynamics differ at the specification level.

The differences that cause measurable behavioral divergence:

Reset semantics: subtract-from-threshold vs zero-reset
→ different membrane trajectories after every spike

Leak ordering: (leak → integrate → fire) vs (integrate → fire → leak)
→ numerical differences that compound across timesteps

Delay model: per-synapse vs per-layer vs none
→ different temporal structure in multi-layer networks

Weight precision: int8 vs int4 vs binary
→ different classification boundaries

Without a shared intermediate representation and a validated test suite, "porting" a model from one chip to another requires full re-characterization. This is not a workflow problem — it is a specification problem. Chips do not share a common SNN behavioral contract.

THRINDEX's Graph IR and .thx artifact format define such a contract for the compiler's output. Backends that pass the open conformance suite are verified to produce conformant temporal dynamics on the reference fixtures. The long-term goal is that "passes THRINDEX conformance" carries the same meaning as "OpenCL conformant" or "Vulkan conformant" in graphics — a publicly verifiable, reproducible claim about what a chip can execute.

What it doesn't solve: Conformance certifies behavior on the test distribution. Hardware-specific optimizations (fused operations, custom learning rules, sparse weight formats) are outside scope and remain the chip vendor's domain.

Without a shared intermediate representation and a validated test suite, "porting" a model from one chip to another requires full re-characterization. This is not a workflow problem — it is a specification problem. Chips do not share a common SNN behavioral contract.

THRINDEX's Graph IR and .thx artifact format define such a contract for the compiler's output. Backends that pass the open conformance suite are verified to produce conformant temporal dynamics on the reference fixtures. The long-term goal is that "passes THRINDEX conformance" carries the same meaning as "OpenCL conformant" or "Vulkan conformant" in graphics — a publicly verifiable, reproducible claim about what a chip can execute.

What it doesn't solve: Conformance certifies behavior on the test distribution. Hardware-specific optimizations (fused operations, custom learning rules, sparse weight formats) are outside scope and remain the chip vendor's domain.

Install. Run a template. Inspect the raster. No hardware. No account.

pip install thrindex

Install. Run a template. Inspect the raster. No hardware. No account.

pip install thrindex

Install. Run a template. Inspect the raster. No hardware. No account.

pip install thrindex